1. Field of the Invention
The present invention relates to a method for accessing a multilevel nonvolatile memory device of the flash NAND type.
2. Description of the Related Art
As known, flash memories of the multilevel type are particularly delicate as regards reliability, due to the fact that each cell may store four different threshold voltage levels, instead of two, as in single level memories. In fact, the increase of the threshold voltage levels to be stored in each cell causes a reduction in the safety margins between contiguous threshold voltage distributions during reading, when it is necessary to discriminate a stored threshold among four possible ones, instead of between only two.
In view of the above, all the circuits and respective control algorithms are designed so as to ensure the correct operation of memories of the considered type. However, the present solutions do not exploit the higher design complexity in order to improve the memory reliability, instead of or in addition to only the access speed, using simple, quick and reliable measures.
In order to clarify this problem, reference is made to FIGS. 1 and 2, showing respectively the threshold voltage distributions of a single-level memory and a two-level memory. As shown in FIG. 1, in case of storing a single bit, just two voltage distributions are present, one for storing logical level “1” and one for storing logical level “0”. Reading may be carried out comparing the stored threshold voltage with a reading voltage VR; and reading may be carried out with a safety margin Δ1 between the reading voltage VR and each voltage distribution.
For a two-bit, four level memory, four voltage distributions are necessary, each for a different state A, B, C and D, e.g., corresponding to logical level “00”, “01”, “10” and “11”. Reading requires comparison of the stored threshold voltage with three different reading voltages VR1, VR2, VR3, and the safety margin is here Δ2, lower than Δ1.
The above problem of data reliability is particularly felt when reading specific data, correctness whereof must be ensured with an even higher precision. This is the case for example of the data stored in the so-called “sector 0” (sector with address 00h) which generally stores the boot information for the system using the memory device.
Presently, the only way to ensure a higher reliability of the “sector 0” is to introduce substitution algorithms which logically remap the content of the “sector 0” in another redundancy sector when, during the EWS (Electrical Wafer Sorting) test, problems are encountered in the physical sector implementing the “sector 0”. This solution does not affect however the safety margins, so that “sector 0” (either the original one or the redundancy one) is read with the same accuracy and reliability as standard sectors of a multilevel memory, lower than for single-bit memories.